System Development for Verification of General Purpose Input Output

In SoC no. of IP block inside it depends upon specific application, increase in the Ip block increases no. of digital control lines causes increase in the size of the chip. GPIO helps internal IP blocks to share digital control lines using MUX and avoids additional circuitry. Since design productivity cannot follow the pace of nanoelectronics technology innovation, it has been required to develop various design methodologies to overcome this gap. In system level design, various design methodologies such as IP reuse, automation of platform integration and verification process have been proposed. GPIO configuration register decides in which mode system has to work GPIO has four modes i.e input, output, functional, interrupt. As per operation particular mode is selected and the operation get performed. Devices with pin scarcity like integrated circuits such as system-on-a-chip, embedded and custom hardware, and programmable logic devices cannot compromise with size can perform well without additional digital control line circuitry.